View CS5841_2803659.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

lcd panel timing controller (14") CS5841 block diagram century semiconductor inc. general description features (continued) features usa: 1485 saratoga ave. #200 san jose, ca, 95129 tel: 408-973-8388 fax: 408-973-9388 sales@century-semi.com sales@century-semi.com.tw www.century-semi.com rev.0.2 september 2000 page 1 of 17 century semiconductor, inc. taiwan: no. 2, industry east rd. 3rd, science-based industrial park, hsin-chu, taiwan tel: 886-3-5784866 fax: 886-3-5784349 ? interface (5v/3.3v[cmos] input, 3.3v[cmos] out- put) ? 6-bit data single-port input, dual-port output. ? timing adjustable for horizontal clock output ? odd pixel, even pixel rgb data out switchable ? correspondent to control timing & specific resolu- tion for different driver ic by changing a mask: 1. can vary the pulse width & starting position of lp signal and pol signal polarity position changed along with lp signal 2. can vary the pulse width & starting position of clkv signal and clkv w time ? control asic output timing design is based on data enable signals ? resolution auto detect for svga, xga and sxga ? embedded power on reset circuits, vth=2.1v, tol- erance 0.3v ? esd spec. 4kv ? power on latch up 200ma/7.5v ? single 3.3v supply ? 100-pin tqfp package (same as m65476bfp) CS5841 is a tft-lcd timing controller, which is applicable to 6-bit data xga (1024*768), sxga (1280*1024) and svga (800*600). CS5841 can update the response timing for display mode of xga, sxga and svga automatically. CS5841 provides a selectable polarity check function to inverse output data for emi reducing, dena vd hd dclki invi pndclk pnhvd pnclkh pninv icmd1 icmd0 svmd vxmd oeswap selclkh set test dl(2~1) gt(2~1) gi(5~0) ri(5~0) bi(5~0) power on reset input selector pol generator stv/clkv generator lp generator sth/clkh generator delay sample polarity output selector data-path clkv stv clkh sth lp pol odgo(5~0) evgo(5~0) odro(5~0) evro(5~0) odbo(5~0) evbo(5~0) invo CS5841
CS5841 century semiconductor inc. page 2 of 17 pin connection diagram figure-1 100-pin tqfp 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 vdd dena vd hd b15 b14 b13 b12 b11 b10 vss g15 g14 g13 g12 g11 g10 vdd r15 r14 r13 r12 r11 r10 vss 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 vdd clkh vss pol evbo0 evbo1 evbo2 evbo3 evbo4 evbo5 vdd evgo0 evgo1 evgo2 evgo3 evgo4 evgo5 vss evro0 evro1 evro2 evro3 evro4 evro5 vss CS5841 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 vdd dclki vss invi pndclk pnhvd pnclkh pninv icmd1 icmd0 svmd vxmd vss oeswap selclkh set test dl1 dl2 gt1 gt2 vdd clkv stv vdd vss sth odbo0 odbo1 odbo2 odbo3 odbo4 odbo5 vdd odgo0 odgo1 odgo2 odgo3 odgo4 odgo5 vdd odro0 odro1 odro2 odro3 odro4 odro5 invo lp vss
CS5841 century semiconductor inc. page 3 of 17 pin description pin i/o pin count description note dena (pin 2) i 1 data enable input. ?h? = input data valid. 48.5khz vd (pin 3) i 1 vertical sync signal input. 60hz hd (pin 4) i 1 horizontal sync signal input. 48.5khz bi(0~5) pin 10~5 i6 blue pixel data input. 32.5mhz gi(0~5) pin 17~12 i6 green pixel data input. 32.5mhz ri(0~5) pin 24~19 i6 red pixel data input. 32.5mhz dclki (pin 27) i1 dot clock input. 65mhz invi (pin 29) i 1 rgb data inverse control signal input ?h? means rgb data input to asic has been inverted. ?l? means non-inverted. 32.5mhz pndclk (pin 30) i 1 dot clock (dclk) polarity setting control input ?l? = dclk rising edge latch input data. ?h? = falling edge latch input data. dc pull-up pnhvd (pin 31) i 1 horizontal & vertical sync signal polarity setting ?l? means hd, vd are active low. ?h? means hd, vd are active high. dc pull-up pnclkh (pin 32) i 1 setting latching edges for source driver ?l? = clkh falling edge latch output data. ?h? = clkh rising edge latch output data. dc pull-up pninv (pin 33) i 1 polarity function calculation set. ?h? = calculated, ?l?= un-calculated. dc pull-up icmd1 (pin 34) i1 driver selection icmd 1 icmd0 corresponding driver ic dc pull-up h h hitachi hd66322 icmd0 (pin 35) i 1 h l ti tmc57561 (sharp l168) dc pull-up l l matsushita mn838814 svmd (pin 36) i 1 no connection dc pull-up vxmd (pin 37) i 1 data output buffer drive circuit switch select. ?l? ? i ol = 4ma normal. ?h? ? i ol = 6ma normal. dc pull-up oeswap (pin 39) i 1 odd pixel, even pixel rgb data output exchange select. ?l? = odd (ro, go, bo) output even pixel rgb data. even (ro, go, bo) output odd pixel rgb data. ?h? = odd (ro, go, bo) output odd pixel rgb data. even (ro, go, bo) output even pixel rgb data. dc pull-up selclkh (pin 40) i 1 clkh output buffer drive circuit switch select. ?l? ? i ol = 6ma normal. ?h? ? i ol = 10ma normal. dc pull-up
CS5841 century semiconductor inc. page 4 of 17 pin i/o pin count description note set (pin 41) i 1 asic internal reset setting input, is usually open. dc pull-low test (pin 42) i 1 test pin, usually open. dc pull-low dl(1~2) (pin 43,44) i 2 adjust clock timing (clkh) for source driver. 4 steps: 2.5ns each step, 0~7.5ns. dc pull-up gt(1~2) (pin 45,46) i 2 adjust clock timing (clkv) for gate driver. 4 steps: 0.5us each step, 1.5~3.0us. dc pull-up clkv (pin 48) o1 output clock for gate driver. i ol = 3ma normal 48.5khz 24pf stv (pin 49) o1 output start pulse for gate driver input. i ol = 3ma normal 60hz 66pf evro(0~5) (pin 57~52) o 6 red even pixel output. i ol = 6ma normal 16.25mhz 60pf evgo(0~5) (pin 64~59) o 6 green even pixel output. i ol = 6ma normal 16.25mhz 60pf evbo(0~5) (pin 71~66) o 6 blue even pixel output. i ol = 6ma normal 16.25mhz 60pf pol (pin 72) o 1 polarity reversed signal output for source driver output, used for dot reversion. i ol = 3ma normal 24.25khz 60pf clkh (pin 74) o 1 output clock for source driver. selclkh = ?l? i ol = 6ma normal, selclkh = ?h?. i ol = 10ma 32.5mhz 60pf lp (pin 77) o1 source driver output control. i ol = 3ma normal 48.5khz 60pf invo (pin 78) o 1 data polarity control signal output. ?h? means asic output rgb data has been reversed. ?l? means unreversed. i ol = 6ma normal 16.25mhz 60pf odro(0~5) (pin 84~79) o6 red odd pixel output. i ol = 6ma normal 16.25mhz 60pf pin i/o pin count description note odgo(0~5) (pin 91~86) o 6 green odd pixel output. i ol = 6ma normal 16.25mhz 60pf odbo(0~5) (pin 98~93) o 6 blue odd pixel output. i ol = 6ma normal 16.25mhz 60pf sth (pin 99) o1 source driver ic start pulse output. i ol = 3ma normal 48.5khz 60pf vdd(pin 1, 18, 26, 47, 50, 65, 75, 85, 92) v supply 3.3v 10%. vss (pin 11, 25, 28, 38, 51, 58, 73, 76, 100) g gnd.
CS5841 century semiconductor inc. page 5 of 17 operating environment maximum operating frequency: 80mhz clock duty: 50 10% voltage range: 3.3 0.3v operating temperature range: -25~75 c (storage temperature range: -55~150 c).
CS5841 century semiconductor inc. page 6 of 17 electrical characteristics 1. absolute maximum ratings: note: the component will be damaged if exceed the absolute maximum condition. normal function operating condition is as below: 2. normal operating condition: note: under normal operation, the function of asic ic must be normal. 3. dc characteristic signal dc specification (according to normal operating condition) note: 1. power off minimum current, all inputs must be v cc or gnd. note: 2. testing consumption current i ccr output cascade 1k ? ? ? ? & 60pf capacitor (one end grounded). symbol parameter min typ max unit v cc power supply -0.3 6.0 v v i signal input voltage -0.3 - v cc +0.3 v v o signal output voltage -0.3 - v cc +0.3 v t a operating ambient -25 - 85 c t stg storage temperature -55 - 150 c p pd power dissipation --1 ? symbol parameter min typ max unit v cc supporting voltage 3.0 3.3 3.6 v t a operating ambient 02575 c symbol parameter condition min typ max unit v oh output voltage high 2.4 - - v v ol output voltage low --0.2v i il input leakage current -10 - 10 a i ol output leakage current high impedance -100 - 100 a i oh output high current (cck) v out =v oh ma i ol output low current (cck) v out =v ol 6(10) ma i oh output high current (all others) v out =v oh ma i ol output low current (all others) v out =v ol 6 ma i ccr current consumption @3.3v v cc dclk=65mhz - 80 100 ma i pd power off current note 1 1.2 ma
CS5841 century semiconductor inc. page 7 of 17 input timing specificaiton symbol item specification unit min typ max input clock - 65 80 mhz t(dclki) input clock period 12 - ns twl(dclki) input clock high time 5 - - ns twh(dclki) input clock low time 5 - - ns tst(di) input data setup time 3 - - ns thd(di) input data hold time 2 - - ns tst(invi) input data reverted control signal setup time 3 - - ns thd(invi) input data reverted control signal hold time 2 - - ns tst(dena) input data enable setup time 3 - - ns thd(dena) input data enable hold time 2 - - ns tst(hd) horizontal sync signal setup time 3 - - ns thd(hd) horizontal sync signal hold time 2 - - ns tst(vd) vertical sync signal setup time 3 - - ns tht(vd) vertical sync signal hold time 2 - - ns tbh(dena) input data enable width (?h?) 800 1024 1280 clk input data enable horizontal blanking time 50 - - clk horizontal sync signal width (?l?) 1 - - clk horizontal front porch 0 - - clk horizontal pack porch 1 - - clk input data vertical blanking time 3 - - h vertical sync signal width (?l?) 1 - - h vertical front porch 2 - - h vertical pack porch 1 - - h
CS5841 century semiconductor inc. page 8 of 17 figure-2 figure-3 twh(dclki) twl(dclki) dclki invi tst(invi) thd(invi) invalid data data ri,gi,bi tst(di) thd(di) invalid data data tst(dena) thd(dena) dena t(dclki) twh(dclki) twl(dclki) dclki invi tst(invi) thd(invi) invalid data data ri,gi,bi tst(di) thd(di) tst(dena) thd(dena) dena invalid data data
CS5841 century semiconductor inc. page 9 of 17 figure-4 figure-5 dclki vd dclki hd thd(vd) tst(vd) thd(hd) tst(hd) tw(vd) vd tf(vd) tb(vd) tbh(denav) dena tw(hd) tf(hd) tb(hd) tbh(denah) hd dena tw(dena)
CS5841 century semiconductor inc. page 10 of 17 horizontal output specification 1-1 icmd0 = ?h?(open)-hitachi hd66322 pndclk, pnhvd = ?h?, pnclkh = ?l?, icmdi = ?h?(open) figure-6 clkv w : 1.5us ~3.0us (0.5us pitch) clkv w = 1.5us gt2 = l, gt1 = l clkv w = 2.0us gt2 = l, gt1 = h. clkv w = 2.5us gt2 = h, gt1 = l clkv w = 3.0us gt2 = h, gt1 = h. note: 1us = 33clkh = 66dclk, at 65mhz: input clock. horizontal output specification 1-2 icmd0 = ?l?(ti tms57561) pndclk, pnclkh, pnhvd = ?h?, icmdi = ?h" figure-7 iclkh 1 clkh last 512 blanking data iclkh 3clkh 1 us+3clkh 0.5us clkv w 10us(330clkh) ro.go.bo (each 6bit) invo sth lp pol clkv clock stops 1 2 iclkh clkh last 512 blanking data iclkh 3clkh 1 us+3clkh clkv w 10us(330clkh) ro.go.bo (each 6bit) invo sth lp pol clkv clock stops 1 1 clkh 0.5 clkh 1 2
CS5841 century semiconductor inc. page 11 of 17 horizontal output 1-3 icmd0=?l-- ( matsushita mn838814 ) ) ) ) pndclk, pnclkh, pnhvd=?h?, icmdi=?l figure-8 iclkh clkh last 512 blanking data iclkh 0.5clkh 1 us+3clkh clkv w 10us(330clkh) ro.go.bo (each 6bit) invo sth lp pol clkv clock stops 1 1 clkh 0.5 clkh 1 2
CS5841 century semiconductor inc. page 12 of 17 horizontal output 2-1 (data output specification) figure-9 symbol item specification unit min typ max t(clkh) horizontal output clock period 25 ns twh horizontal output clock high time 10 ns twl horizontal output clock low time 10 ns tst1 output data set-up time 6 ns thd1 output data hold time 6 ns t(clkh) twh twl clkh (pnclkh=?l?) output data (r.g.b.& invo) clkh (pnclkh=?h?) ns twl twh data tst1 thd1
CS5841 century semiconductor inc. page 13 of 17 vertical output specification figure-10 ivd vd 1 2 3 4 767 769 ihd 767 768 769 ihd ihd 330 clkh stv(frm) clkv hd dena stv clkv 768
CS5841 century semiconductor inc. page 14 of 17 clkv, stv timming specification figure-11 ac timing : : : : symbol item specification unit min typ max tst(stv) stv set-up time 3 s thd(stv) stv hold time 3 s tw(h) clkv high 10 s tw(l) clkv low 5 s tw(h) tw(l) clkv tst(stv) thd(stv) 1 2 stv
CS5841 century semiconductor inc. page 15 of 17 data polarity figure-12 as phinv presents ?h?, polarity starts to work. asic will compare with previous data output before outputting r.g.b data (even, odd 36 bit). as the number of bits changed exceeds 18, asic will invert r.g.b data, then outputs the inverted data, and ultimately eliminates emi by reducing the bit numbers changed between two asic?s outputs and keeping the bit numbers changed below half of total data output. above is the polarity diagram, output data a implies: the original output data has not been calculated by polarity, including r.g.b. even & odd data, each 18 bits. output data b implies the actual data has been polarity calculated. invo output indicates whether the process (from data a converted to data b) has been inverted. driver ic can convert the received data b to the original data a by using invo signal. below is the polarity chart: data output: 1. the rise time of data output from low (10% vdd) to high (90%vdd): 4ns 2. odd ro (0~5) and invo delay 0ns, even ro (0~5) delay 1ns, odd go (0~5) delay 2ns, even go (0~5) delay 3ns, odd bo (0~5) delay 4ns, even bo (0~5) delay 5ns, r.g.b. data output group has time difference during output. bit numbered changed invo output output data b 19 bit and above h data a inverted 18 bit below l data a non-reverted data1 data2 data3 1b 2b 3b 1a 2a 3a clkh output data a (36bit) output data b (36bit) ivno output bit number changed for output data a & data b bit number changed for output data a & data b
CS5841 century semiconductor inc. page 16 of 17 package outline (100-pin tqfp) symbol dimensions in millimeters dimensions in inches min nom max min nom max a - - 1.2 - - 0.047 a1 0.05 - 0.15 0.002 - 0.006 a2 0.95 1 0.15 0.037 0.039 0.041 b 0.13 0.16 0.23 0.005 0.006 0.009 c 0.09 - 0.2 0.004 - 0.008 d - 14 - - 0.551 - d1 - 12 - - 0.472 - e - 14 - - 0.551 - e1 - 12 - - 0.472 - e - 0.40 - - 0.016 - l 0.45 0.60 0.75 0.018 0.024 0.030 l1 - 1 - - 0.039 - 03.5 7 03.5 7 1 25 26 50 51 75 76 100 e b a1 a c l l1 a2 d d1 e e1
CS5841 century semiconductor inc. page 17 of 17 application circuit schematic figure-13 using 100-pin tqfp package r46 10k vs1 b4 r3 br4 swap +3.3v b4 b3 gt2 r51 r + c40 10u g0 b4 br10 br2 g4 ivv g0 r49 10k g3 br9 g4 r1 dclk b2 b4 r4 dclk +3.3v +3.3v ena1 r57 r g2 br15 sdclk r1 g3 br14 c41 0.1u r4 b2 b5 b2 r54 10k r4 c37 0.1u md0 c35 0.1u r52 r b1 r55 r b0 b5 r3 b0 br6 CS5841 u5 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 100 vdd dena vd hd b15 b14 b13 b12 b11 b10 vss g15 g14 g13 g12 g11 g10 vdd r15 r14 r13 r12 r11 r10 vss vdd dclki vss invi pndclk pnhvd pnclkh pnivv icmd1 icmd0 svmd vxmd vss oeswap selclkh set test dl1 dl2 gt1 gt2 vdd clkv stv vdd vdd clkh vss pol evbo0 evbo1 evob2 evob3 evob4 evob5 vdd evgo0 evgo1 evgo2 evgo3 evgo4 evgo5 vss evro0 evro1 evro2 evro3 evro4 evro5 vss sth odbo0 odbo1 odbo2 odbo3 odbo4 odbo5 vdd odgo0 odgo1 odgo2 odgo3 odgo4 odgo5 vdd odro0 odro1 odro2 odro3 odro4 odro5 invo lp vss vss b2 g5 r41 100 b1 +3.3v ena1 int g1 g4 r5 g1 g4 r50 10k s1 +3.3v vs1 +3.3v test ext b0 c43 0.1u hvd ena1 dl1 hs1 r58 r md1 g2 br7 r5 r42 100 u6 lx8117 1 2 3 vi gnd vo r1 b5 r43 100 r44 10k r3 c32 0.1u set hs1 c36 0.1u b1 jp5 odod 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 g1 gt1 jp4 conn pwr 1 2 r0 r5 br11 r0 b5 c38 0.1u +3.3v r0 + c42 10u b3 vs1 g3 r0 g5 g2 b0 ext +3.3v r53 10k jp31 pwr 1 2 3 g0 +3.3v r4 b1 c39 0.1u g3 br12 g2 r47 10k c31 0.1u +3.3v r48 10k jp6 con25 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 r56 r hs1 invi hs1 r2 r45 10k dl2 +3.3v r2 clkh +3.3v r3 g5 b3 c34 0.1u br3 ena1 jcp2 digit input 21 22 23 24 25 19 20 5 4 3 2 1 12 11 10 9 8 7 6 18 17 16 15 14 13 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 r2 clkh g0 br5 br1 br13 r2 b3 c33 0.1u br8 g5 g1 vs1 r1 r5

▲Up To Search▲

Price & Availability of CS5841

	To Download CS5841 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .